The present invention relates, in general, to semiconductor devices, and more particularly, to devices formed in compound semiconductor substrates sensitive to performance variations as a result of changes in operational temperature.
One problem that is common to conventional field effect transistors (FETs) formed in compound semiconductor substrates is that their performance tends to vary with changes in operational temperature. For example, the current flow from a drain region to a source region of the FET can vary as the semiconductor device is heated or cooled. This variation in the performance of the FET is further illustrated in FIG. 1.
FIG. 1 is a graph 10 demonstrating how the performance of a field effect transistor fabricated using conventional processing techniques can vary as the FET is heated and cooled. Graph 10 has an x-axis 11 that represents a voltage potential between a gate structure and a source region of the FET in volts (V). Typical values for this gate to source voltage (V.sub.gs) can range from about -10 volts to +10 volts depending on the design of the individual FET. Graph 10 also has a y-axis 12 that represents the drain to source current (I.sub.ds) of the FET in milliamps (mA). A line 13 represents the drain to source current of the conventional FET as the gate to source voltage is varied. As the gate to source voltage is varied, the FET is maintained at room temperature (approximately 25 degrees Celsius (.degree. C.)). Lines 14 and 15 represent the drain to source current of the same FET over the same voltage range, but at an ambient temperature of 90.degree. C. and -40.degree. C., respectively.
As shown in graph 10, the drain to source current for the FET at the same gate to source voltage potential can vary significantly depending on the operational temperature. For example, a bracket 16 represents the variance in drain to source current of the FET at a gate to source voltage potential of about -2.6 volts. Such performance variations are unacceptable as FETs are commonly placed in environments where the operational temperature can vary significantly.
One traditional technique for addressing this problem is to add temperature compensating diodes to the field effect transistor. These temperature compensating diodes are either integrated into the semiconductor device or are discrete components that are added to the semiconductor device after fabrication. The addition of the temperature compensating diodes can complicate the design of the FETs or increase the surface area of the devices to make room for the diodes. Additionally, if the temperature compensating diodes are discrete components, then they complicate the manufacturing process and add a reliability concern for the FET. Consequently, the use of temperature compensating diodes increases the manufacturing cost of field effect transistors formed in compound semiconductor substrates.
Accordingly, a need exists to provide a semiconductor device formed in a compound semiconductor substrate that is more tolerant of variations in operational temperature. It would also be advantageous if the semiconductor device did not require the use of temperature compensating diodes, and it would be advantageous if the semiconductor device could be formed within less surface area than conventional FETs.